收藏本站
AT45DB642
Memory Architecture Diagram
SECTOR ARCHITECTURE
BLOCK ARCHITECTURE
PAGE ARCHITECTURE
SECTOR 0 = 8 Pages
8448 bytes (8K + 256)
SECTOR 0
BLOCK 0
BLOCK 1
8 Pages
PAGE 0
PAGE 1
BLOCK 2
SECTOR 1 = 248 Pages
261,888 bytes (248K + 7936)
PAGE 6
BLOCK 30
PAGE 7
SECTOR 2 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 31
BLOCK 32
PAGE 8
PAGE 9
BLOCK 33
SECTOR 3 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 62
BLOCK 63
BLOCK 64
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 31 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 32 = 256 Pages
BLOCK 65
PAGE 8189
270,336 bytes (256K + 8K)
BLOCK 1022
BLOCK 1023
Block = 8448 bytes
(8K + 256)
PAGE 8190
PAGE 8191
Page = 1056 bytes
(1K + 32)
Device
Operation
Read Commands
The device operation is controlled by instructions from the host processor. The list of instruc-
tions and their associated opcodes are contained in Tables 1 through 4. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired
buffer or main memory address location. While the CS pin is low, toggling the SCK/CLK pin
controls the loading of the opcode and the desired buffer or main memory address location
through either the SI (serial input) pin or the parallel input pins (I/O7 - I/O0). All instructions,
addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to
denote the 11 address bits required to designate a byte address within a buffer. Main memory
addressing is referenced using the terminology PA12 - PA0 and BA10 - BA0, where PA12 -
PA0 denotes the 13 address bits required to designate a page address and BA10 - BA0
denotes the 11 address bits required to designate a byte address within the page.
By specifying the appropriate opcode, data can be read from the main memory or from either
one of the two SRAM data buffers. The DataFlash supports two categories of read modes in
relation to the SCK/CLK signal. The differences between the modes are in respect to the inac-
tive state of the SCK/CLK signal as well as which clock cycle data will begin to be output. The
two categories, which are comprised of four modes total, are defined as Inactive Clock Polarity
Low or Inactive Clock Polarity High and SPI Mode 0 or SPI Mode 3. A separate opcode (refer
to Table 1 for a complete list) is used to select which category will be used for reading. Please
refer to the “ Detailed Bit-level Read Timing ” diagrams in this datasheet for details on the clock
cycle sequences for each mode.
3
1638F – DFLSH – 09/02
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
AT88CK9000-8TH CRYPTO PROGRAMMER BOARD 8-TSSOP
AT88SC12816C-MJ IC EEPROM 128KBIT 1.5MHZ M2J
AT88SC25616C-MJ IC EEPROM 256BIT 1.5MHZ M2J
AT88SC3216C-MJ IC EEPROM 32KBIT 1.5MHZ M2J
AT88SC6416C-MJ IC EEPROM 64KBIT 1.5MHZ M2J
AT91EB40A KIT EVAL FOR ARM AT91R40008
AT91EB42 KIT EVAL FOR ARM AT91M42800A
AT91EB55 KIT EVAL FOR ARM AT91M55800A
相关代理商/技术参数
AT45DB642-TI 功能描述:闪存 64M bit RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel
AT45DB64D2-CNU 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:32-bit Microcontrollers
AT45DCB002 功能描述:存储卡 2M bit RoHS:否 制造商:Olimex Ltd. 产品:SD 存储容量: 连续读取: 连续写入: 有源模式电流: 工作电源电压: 最大工作温度: 尺寸:
AT45DCB002D 功能描述:存储卡 CARD 2M BYTE RoHS:否 制造商:Olimex Ltd. 产品:SD 存储容量: 连续读取: 连续写入: 有源模式电流: 工作电源电压: 最大工作温度: 尺寸:
AT45DCB004 功能描述:DATAFLASH CARD 4MEGABYTE RoHS:否 类别:存储卡，模块 >> 存储器，PC 卡 系列:- 标准包装:30 系列:- 存储容量:8GB 存储器类型:存储卡 - Extreme III SD?
AT45DCB004C 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:4-megabyte 2.7-volt DataFlash Card
AT45DCB004C_06 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:4-megabyte 2.7-volt DataFlash Card
AT45DCB004D 功能描述:存储卡 CARD 4M BYTE RoHS:否 制造商:Olimex Ltd. 产品:SD 存储容量: 连续读取: 连续写入: 有源模式电流: 工作电源电压: 最大工作温度: 尺寸: